Agnus: The Amiga's Memory Master

Overview

Agnus was the Amiga’s traffic controller. Every memory access—from the 68000, the Blitter, the display hardware, audio playback—flowed through Agnus. It allocated time slots fairly, ensuring smooth graphics and audio while letting the CPU work during the gaps.

Fast facts

Function: DMA controller, Blitter engine, Copper coprocessor.
Versions: 8361 (NTSC), 8367 (PAL), 8370/8372 (Fat Agnus), 8375 (Super Agnus).
Chip RAM: 512KB (original), 1MB (Fat), 2MB (Super/ECS).
DMA channels: 25 independent channels for different purposes.

DMA slot allocation

Agnus divides each scanline into time slots. The standard PAL/NTSC layout interleaves memory refresh with disk on the early slots:

Slots	Purpose
0, 2, 4	Memory refresh (DRAM)
1, 3, 5	Disk DMA
7, 9, 11, 13	Audio channels 0-3
15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45	Sprites 0-7 (two slots each)
0x38-0xD0 (display window)	Bitplane DMA
Remaining	Copper, Blitter, CPU

Outside bitplane DMA the CPU and Blitter alternate cycles by default — odd cycles for the CPU, even for the Blitter — so the Blitter operates concurrently with the CPU rather than starving it. Setting the BLITHOG bit (BLTCON1 bit 1) gives the Blitter every available cycle, halting the CPU until the blit completes; this is faster but blocks CPU work, so games tend to leave BLITHOG clear unless the blit is short.

Full DMA priority chain

When multiple DMA channels need the same cycle, Agnus arbitrates in this fixed order (highest to lowest):

Memory refresh
Disk
Audio
Sprites (during sprite DMA window)
Bitplanes (during display window)
Copper
Blitter
CPU (gets whatever slots remain)

Chip versions

Chip	Chip RAM	Notes
8361/8367	512KB	Original A1000, early A500
8370/8372	1MB	“Fat Agnus” - larger package
8375	2MB	ECS “Super Agnus”
Alice	2MB	AGA replacement in A1200/A4000

The Blitter

The Blitter is a DMA engine within Agnus that performs:

Block copies: rectangular memory moves.
Logic operations: combine up to three sources with minterm logic.
Area fill: flood-fill between edges.
Line drawing: hardware-accelerated lines.

Blitter sources

Source	Purpose
A	Source/mask data
B	Source data
C	Destination read (for merge)
D	Destination write

Minterm operations

The Blitter combines sources using an 8-bit minterm value:

Result = (A AND B AND C) * bit7 +
         (A AND B AND NOT C) * bit6 +
         ... and so on for all 8 combinations

Common minterms:

$F0: Copy A to D (ignore B, C)
$CA: Cookie-cut (A masks B onto C)
$5A: XOR A with C

The Copper

The Copper is a coprocessor with just three instructions:

Instruction	First-word bit 0	Second-word bit 0	Purpose
MOVE	0	(don’t care)	Write to register
WAIT	1	0	Wait for beam position
SKIP	1	1	Skip next instruction if beam past position

WAIT and SKIP share the same first-word encoding; the second word’s low bit distinguishes them.

Copper list example

dc.w    $0180, $0000    ; COLOR00 = black
dc.w    $2c07, $fffe    ; WAIT for line $2c
dc.w    $0180, $0f00    ; COLOR00 = red
dc.w    $5007, $fffe    ; WAIT for line $50
dc.w    $0180, $00f0    ; COLOR00 = green
dc.w    $ffff, $fffe    ; End (wait forever)

Copper capabilities

Palette changes: different colours per scanline (copper rainbows).
Mode switches: change resolution mid-screen.
Sprite repositioning: move sprites to different locations per frame.
Register pokes: modify nearly any hardware register.

Key registers

Register	Address	Purpose
DMACON	$DFF096	DMA control
DMACONR	$DFF002	DMA control read
BLTCON0	$DFF040	Blitter control
COP1LC	$DFF080	Copper list 1 pointer
COP2LC	$DFF084	Copper list 2 pointer
COPJMP1	$DFF088	Restart Copper list 1

DMA controller, Blitter, and Copper in one package