Zilog Z80

The Zilog Z80 is an 8-bit microprocessor designed by Federico Faggin — the engineer who led the Intel 4004 and 8080 projects before leaving Intel in 1974 to co-found Zilog. The Z80 launched in 1976 as a deliberate improvement on the 8080: binary-compatible at the opcode level, but with a richer register file, more addressing modes, simpler interface logic (single 5V supply, single-phase clock), and integrated DRAM refresh — features that, combined with aggressive pricing, made the chip the default choice for European 8-bit home computers and a major presence in 1980s arcades.

The Z80 powered the ZX Spectrum, Amstrad CPC, MSX, Sega Master System, Game Gear, the original Game Boy (Sharp LR35902 — a Z80 variant), TRS-80, and a generation of CP/M business machines. For most British and European bedroom coders of the 1980s, “learning machine code” meant learning Z80.

Two registers nobody else had

The Z80 carries “two special-purpose registers generally not found in other 8-bit microprocessors”: the interrupt vector register I and the memory refresh register R. Neither exists for the programmer’s benefit. Both were repurposed by programmers anyway, and between them they explain a surprising amount of British computing.

R counts DRAM refresh, in time that was going spare. Dynamic memory forgets unless every row is re-read periodically, which normally costs a machine external counters and stolen cycles. Zilog put the counter on the CPU and paid for it with nothing:

The time during T3 and T4, when the Z80 decodes the instruction internally and the address bus would otherwise be idle, is used in Z80-based systems for refreshing the dynamic memories. This process is called transparent refresh.

The refresh happens in the half of each fetch when the processor is thinking rather than addressing. It is the same idea the Amiga would later build a whole machine around — find the cycles a device is not using and give them to something else — arriving in 1976 inside a single chip.

R is “an 8-bit register which is used as a 7-bit counter”, incremented after every opcode fetch. That combination — visible to software, changing constantly, free to read — made it the 8-bit world’s cheapest source of randomness, and on the ZX81 it does something stranger still: the display hardware watches the refresh address and uses it to fetch the character set. A housekeeping counter, generating a television picture.

I supplies half an address. In the Z80’s vectored interrupt mode, “the I register is used to store the high-order eight bits of the 16-bit address; the low-order eight bits must be supplied by the interrupting device”. The processor and the peripheral each contribute half a pointer.

And I has a second job that Zilog documents plainly: “During refresh, the contents of the I Register are placed on the upper eight bits of the address bus.” The same register that routes interrupts also supplies the top half of every refresh address.

That is why, on the Spectrum, where I points decides whether refresh cycles collide with the ULA’s video fetches — the difference between a clean display and snow. Zilog designed I to vector interrupts; Sinclair’s hardware made it a graphics setting.

Halting is not stopping

HALT reads as “stop”, and does not:

This instruction suspends (halts) all operations, and the microprocessor waits until an interrupt or the reset is received. During the halt, the microprocessor continues to execute NOP instruction to maintain memory refresh cycles.

A halted Z80 is still fetching — running NOP after NOP so that R keeps counting and the DRAM keeps its contents. It is idling loudly rather than sleeping, which is exactly what a machine with no refresh hardware of its own requires. Nintendo’s Game Boy manual leans on this instruction for power saving; the ZX81 leans on it to wait for the display.

Sixteen registers in one instruction

The alternate register set is the Z80’s most distinctive addition to the 8080, and the instruction that reaches it costs almost nothing:

EXX … 1 byte, 4 T-states … The contents of the general-purpose registers BC, DE, and HL are exchanged with the contents of their respective alternate registers BC’, DE’ and HL’. Flags: No flags are affected.

Three register pairs swapped in a single byte and four T-states, without disturbing the flags. An interrupt handler on a 6502 machine has to push registers to the stack and pull them back; a Z80 handler can execute EXX, work in a second set of registers entirely, and EXX back. That is why Z80 interrupt code can afford to be short, and why fast loaders and raster effects on Z80 machines are written the way they are.

Fast facts

• Designer: Federico Faggin / Masatoshi Shima / Ralph Ungermann at Zilog, 1974-1976.
• Launched: July 1976.
• Clock speed (original NMOS): 2.5 MHz (Z80), 4 MHz (Z80A), 6 MHz (Z80B), 8 MHz (Z80H). CMOS Z84C00 variants run up to 20 MHz.
• Data bus: 8-bit.
• Address bus: 16-bit (64 KB addressable).
• Process: NMOS (original), CMOS (later Z84C00 series).
• Package: 40-pin DIP for the original; smaller packages for embedded variants.
• 8080 compatibility: binary-compatible superset — most 8080 code runs unmodified.

⚠ Faggin’s authorship of the Z80 is attested in this library only by MC microcomputer, an Italian magazine, which calls him “il padre dello Z80” in 1990. The attribution is not in doubt; the evidence held here is single-source and not in English.

Register architecture

The Z80’s register file was generous for a 1976 8-bit chip — and notably richer than the contemporary 6502:

Register set	Purpose
A, F	Accumulator and flags (combined pair: AF)
B, C, D, E, H, L	General-purpose 8-bit; paired as BC, DE, HL for 16-bit address arithmetic
A’, F’, B’, C’, D’, E’, H’, L’	Shadow registers — swapped in/out via EX AF,AF' and EXX
IX, IY	16-bit index registers with signed displacement: (IX+d), (IY+d)
SP	Stack pointer (16-bit)
PC	Program counter (16-bit)
I	Interrupt vector base (mode 2)
R	DRAM refresh counter (bits 0-6 auto-increment; bit 7 writable)

The shadow set is the Z80’s most distinctive architectural feature. A single-instruction context switch — EXX swaps BC/DE/HL with BC’/DE’/HL’ in 4 T-states — lets interrupt handlers preserve state without a single push/pop. Many Spectrum games and the BASIC ROM use the shadow set for the interrupt routine that maintains the system clock (FRAMES at $5C78, three bytes incremented every frame).

Key instruction families

Family	Examples	What’s notable
Block operations	LDIR, LDDR, CPIR, OTIR	Repeating instruction prefix — one opcode copies up to 64 KB of memory
Bit manipulation	BIT n,r, SET n,r, RES n,r	Single-instruction bit-test on any register or memory location
Relative jumps	JR, JR cc, DJNZ	Signed 8-bit displacement; smaller, faster than absolute JP
Index modes	LD A,(IX+d), INC (IY+d)	Structure-style access via signed 8-bit offset
I/O	IN, OUT, IN A,(C), OUT (C),A	Separate I/O address space (256 ports addressed by low 8 bits)
Conditional return	RET cc	One-byte conditional return — denser than testing-then-RET

For Spectrum work the most-used are DJNZ (16-bit loop counters in 13 T-states, no flag side effects on B), LDIR (the screen-clear primitive), BIT n,(HL) (collision testing against attribute bytes), and the index registers (sprite structures).

Undocumented features

The real silicon supports several instructions that don’t appear in Zilog’s official manual but are universally accepted by assemblers and modelled by accurate emulators:

• Half-registers of IX and IY. IXH, IXL, IYH, IYL are usable as 8-bit operands in any DD- or FD-prefixed opcode. LD IXH, 5 works. This applies only to register operands — LD (IX+d), H still references the real H, not IXH.
• SLL (Shift Left Logical). Like SLA but shifts a 1 into bit 0 instead of 0. Useful occasionally for clean ANDed shifts.
• Undocumented flag effects. Bits 3 and 5 of F (X and Y flags) take their values from various source bytes in ways the official manual doesn’t document. Demo-scene code occasionally relies on these.

The most notorious CPU-family quirk: OUT (C),0 outputs the literal value 0 on NMOS Z80, but outputs 0xFF on the CMOS Z84C00. Software written assuming the NMOS behaviour breaks on CMOS parts and on emulators that model the CMOS variant.

Z80 vs 6502 — temperament

The two dominant 8-bit CPUs of the era have very different personalities:

Feature	Z80	6502
Register count	Many (with shadows + index)	Few (A, X, Y)
Addressing modes	Fewer kinds, but more flexible	Many kinds, all clever
Block operations	Built-in (LDIR)	Must be hand-coded
Code density	More verbose; bigger opcodes	Tighter; smaller routines
Clock per instruction	Higher T-state counts but higher clock	Lower cycle counts at lower clock
Typical Spectrum vs C64	3.5 MHz Z80	1 MHz 6510
Learning curve	Steeper, more to remember	Gentler, easier to fit in your head

Neither was objectively better; the 6502 won on density and elegant addressing, the Z80 won on register richness and useful block instructions. The platform-architecture debate of the 1980s often reduced to a CPU-camp argument.

Systems powered

• Home computers: ZX Spectrum (3.5 MHz), Amstrad CPC (4 MHz), MSX (3.58 MHz), TRS-80 (1.77-4 MHz), Sharp MZ series, Jupiter Ace.
• Consoles: Sega Master System and Game Gear (Z80A at 3.58 MHz); Game Boy (Sharp LR35902 — a Z80 derivative); ColecoVision; Sega Mega Drive (Z80 as audio co-processor for backwards compatibility).
• Arcade: Pac-Man, Galaga, Donkey Kong’s audio sub-board, countless others.
• Business / CP/M: Kaypro, Osborne 1, Amstrad PCW.

Cultural impact

For European bedroom coders, the Z80 was assembly language. British schoolchildren in 1985 learning Hewson’s Hints & Tips for the ZX Spectrum were learning Z80; the Sinclair User “Andrew Hewson’s Helpline” column was a Z80 column under another name. The chip’s instruction set was the entry-level apprenticeship for a generation of UK developers — many of whom went on to ship 16-bit games, then PC games, then triple-A titles, all built on muscle memory first acquired by writing DJNZ loops on a rubber-keyed Spectrum.

Why the Z80 matters for Code Like It’s 198x

Every line of Shadowkeep’s assembly is Z80. The Project teaches the Z80 instruction set not as historical curiosity but as the live language of the Spectrum platform: LDIR for screen clears, BIT n,(HL) for attribute-based collision, DJNZ for tight loops, port I/O via IN A,(C) / OUT (C),A for ULA communication. The chip’s design choices — shadow registers, block operations, relative jumps — shape what idiomatic Spectrum code looks like.

See also

• Federico Faggin — Designer.
• Zilog — Manufacturer.
• ZX Spectrum
• Amstrad CPC
• 6502 — Z80’s rival.
• ULA — The Spectrum’s other key chip.