In our Boolean model, each wire has a value: 0 or 1. We draw 1 as lit and 0 as unlit. A physical signal represents those values, but the drawing does not measure its voltage or model changes while it settles.
A bit is one binary digit. Here the two digits let us describe a gate’s input and output without drawing its internal electronics.
Now put a part in the middle of some wires. Two wires in, one wire out, and a rule saying what comes out for each combination going in.
That rule is a truth table. The part is called a gate.
AND, in wire
Here is the AND table you know, and beside it an interactive model of the rule. Click either input to
change its value, or focus it and press Enter or Space.
Click an input to turn it on or off, and watch the wires.
| A | B | OUT |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Work through all four rows. This checks every input combination in our two-input Boolean model. It does not test every behaviour of a physical chip.
For example, a manufacturer’s AND-gate data sheet has a function table, but also specifies supply conditions, input levels and propagation delay: the time between an input change and its effect at the output. Our drawing leaves those details out. See Texas Instruments’ SNx4HC08 data sheet, sections 5.3, 5.7 and 7.4, for one concrete part.
OR and XOR
The same again, with the other two.
Click an input to turn it on or off, and watch the wires.
| A | B | OUT |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Click an input to turn it on or off, and watch the wires.
| A | B | OUT |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Set both inputs on the XOR and watch the output go out. That is the row where it parts
company with OR, the one Unit 2 of Truth Tables said would be waiting for you.
NOT takes one wire
NOT is the odd one. One wire in, one wire out, and it hands back the opposite.
Click an input to turn it on or off, and watch the wires.
Its output is 1 when its input is 0. Zero is a defined input value in this model, not a disconnected wire.
Why these shapes
The shapes are not decoration. They are a notation, the way a musical stave is, and these are one familiar set of gate symbols. Other schematics may use a different symbol convention.
Worth knowing: the little circle on the NOT gate means inverted. Stick it on the nose of
an AND gate and you have a NAND, which is AND followed by NOT. You will not need that
here, but you will see it, and now it will not be a new symbol.
When it’s wrong, see why
- The output is lit when nothing is going in. That is a
NOT, or a gate with a circle on its nose. Check the shape. - You cannot tell AND from OR in a diagram.
ANDhas a flat back and a round front.ORis curved at both ends and comes to a point. - The circuit does not match the table you meant. Set every row in turn. Four rows cover every input combination in this two-input Boolean model; physical timing and electrical tests are separate.
What you’ve learnt
- Our model gives each wire a bit: 0 or 1.
- A truth table describes a gate’s settled Boolean behaviour.
AND,OR,XORtake two wires in;NOTtakes one.- The small circle means inverted.
- Four rows cover a two-input Boolean model, not all physical behaviour.
If a drawing matches all four AND rows, have we measured a real chip’s delay?
No. We checked its Boolean results. Measuring a physical chip’s delay needs an input change, a time measurement and stated electrical conditions. The interactive drawing does not supply those measurements.
What’s next
Three gates, three tables, nothing new. In Unit 2 we wire two of them up and discover we have accidentally built something that adds.