The Commodore 64 has 64K of RAM, 20K of ROM and 4K of input/output chips, and a processor that can only address 64K. Commodore’s Programmer’s Reference Guide asks the obvious question, “How is this all possible on a computer with a 16-bit address bus, that is normally only capable of addressing 64K?”, and answers it in the next sentence: “The secret is in the 6510 processor chip itself.”
The 6510 is a 6502 with two additions. The first is a small I/O port, read and written at addresses 0 and 1, whose lines switch the ROMs and the I/O chips in and out of the memory map and run the cassette deck. The second is a pin that lets another chip take over the buses, which is how the VIC-II video chip shares memory with it. Everything else, including the instruction set, is the 6502’s. Commodore’s data sheet says the internal architecture is “identical to the Commodore Semiconductor Group 6502 to provide software compatibility”.
Fast facts
- Instruction set: the 6502’s 56 instructions and thirteen addressing modes.
- Registers: accumulator A, index registers X and Y, stack pointer, program counter and status register, all 8 bits except the 16-bit program counter.
- Clock in the C64: 985,248 Hz on PAL machines and 1,022,727 Hz on NTSC ones. Commodore’s data sheet offers 1, 2 and 3 MHz parts.
- I/O port: data direction register at address 0, data register at address 1. The C64’s 6510 brings six port lines out to pins.
- Package: 40-pin DIP.
- Later version: the 8500, fitted to late C64C boards.
What changed from the 6502
A programmer sees the 6502 unchanged: the same three working registers, A, X and Y, each holding one byte, the same stack in page 1 and the same instructions with the same timings. The 6502 entry covers the processor itself.
The changes are on the outside of the chip. The data sheet prints the 6510’s pinout next to two variants. The plain 6510 has port lines P0 to P5 on pins 29 down to 24, and keeps the RDY and NMI inputs. The 6510-1 and 6510-2 bring all eight port lines out, and have no RDY or NMI pins. Commodore’s reference books describe the C64’s port as six lines, and Mapping the Commodore 64 lists bits 6 and 7 as “Not connected”.
The other new pin is AEC, address enable control. When it is low, “the Address Bus, R/W and Data Bus are in a high-impedance state”, which the data sheet says “allows easy DMA and multiprocessor systems”. In the C64 that other user of the bus is the VIC-II. The two chips take turns within each clock cycle: the processor uses the bus in the second half of the cycle and the VIC-II normally in the first. When the VIC-II needs more than its half, on the “badlines” where it reads a row of character codes, it pulls the 6510’s RDY line low to stop the processor. Christian Bauer’s description of the chip explains the three-cycle warning it gives first: RDY is ignored during writes, and “the 6510 never does more than three writes in sequence”. The VIC-II entry covers what that costs.
The clock comes from the VIC-II too. Marko Mäkelä’s measurements, published in C=Hacking in 1995, give the arithmetic: a PAL C64 divides its 17,734,472 Hz crystal by 18 to get 985,248 Hz, and an NTSC one divides 14,318,181 Hz by 14 to get 1,022,727 Hz.
The port at $00 and $01
Location 0 is the data direction register: a 1 bit makes that port line an output, a 0 makes it an input. Location 1 holds the data. Mapping the Commodore 64 names them D6510 and R6510.
| Bit | Name | Direction | Job |
|---|---|---|---|
| 0 | LORAM | output | BASIC ROM or RAM at $A000–$BFFF |
| 1 | HIRAM | output | KERNAL ROM or RAM at $E000–$FFFF |
| 2 | CHAREN | output | I/O chips or character ROM at $D000–$DFFF |
| 3 | output | Cassette write line | |
| 4 | input | Cassette switch sense: reads 0 while a deck button is pressed | |
| 5 | output | Cassette motor: 0 runs the motor |
Bit 4 is the only input, which is why the direction register holds 47 ($2F, binary 101111). The Programmer’s Reference Guide says the C64 sets that value automatically. It also warns that because the same port runs the Datassette, “it is important to affect only the proper bits”. Commodore’s service manual confirms the motor polarity: when bit 5 goes low, the transistors switch current through the motor. (Mapping the Commodore 64 has it the other way round.)
Switching memory
With all three bank bits set, which gives the usual value of $37 (55) in location 1, the machine has BASIC, the KERNAL and the I/O chips in place and 38K of free RAM for BASIC. Clearing bits swaps ROM for the RAM that is always underneath it.
Value in $01 |
What the processor sees | Notes |
|---|---|---|
$37 |
BASIC, KERNAL, I/O | The default map, with “38K contiguous bytes of user RAM” |
$36 |
KERNAL and I/O; RAM at $A000 |
“Intended for use with soft load languages (including CP/M)”, 52K of RAM |
$35 |
I/O only; RAM everywhere else | “60K bytes of RAM and I/O devices. The user must write his own I/O driver routines” |
$34 or $30 |
RAM everywhere | “Access to all 64K bytes of RAM” |
$33 |
BASIC, KERNAL and the character ROM at $D000 |
No I/O while it is switched in |
Two rules explain the table. BASIC needs the KERNAL, so taking HIRAM low removes BASIC as well, whatever LORAM says. And CHAREN only chooses between I/O and the character ROM; in a map with neither, the guide says, “RAM will appear from $D000-$DFFF instead”, which is why $34 and $30 give the same result.
A write to an address where ROM is showing always goes to the RAM underneath. The guide presents this as a feature: “this allows a hi-resolution screen to be kept underneath a ROM, and be changed without having to bank the screen back into the processor address space.” A read still returns the ROM. Mapping the Commodore 64 uses the same rule to copy BASIC into RAM with one line, FOR I=40960 TO 49151:POKE I,PEEK(I):NEXT, then POKE 1,PEEK(1) AND 254 to switch to the copy, which can then be edited: POKE 41122,69 turns the keyword FOR into FER.
Banking has costs. The KERNAL holds the interrupt vectors, so Mapping warns that before switching it out “it is necessary to disable interrupts”, or supply your own vectors at $FFFA–$FFFF. Switching in the character ROM switches out the I/O chips, including the timer that drives the keyboard scan, so Mapping’s routine for copying the character set starts with POKE 56333,127 to stop that interrupt and ends with POKE 56333,129 to restart it.
The port bits are not the whole story. Two lines on the cartridge port, GAME and EXROM, also feed the logic that decides the memory map, so a cartridge can put ROM at $8000 or replace BASIC or the KERNAL. The Programmer’s Reference Guide draws its maps against all four signals, LORAM, HIRAM, GAME and EXROM. There is more on the idea in memory mapping.
The 8500
Later C64C boards use the 8500 in place of the 6510. Commodore’s 1992 service manual lists it on board assembly 250469, alongside the 8580 SID and the 8562 or 8567 video chip, where earlier boards list the 6510.
One difference shows up in the unconnected bits 6 and 7. A 1 written there, with the bit set as an output, is still read back as 1 for a while after the bit is switched to an input, because the charge takes time to leak away. The VICE emulator’s source code gives the averages its authors use: about 350 milliseconds for a 6510 and about 1.5 seconds for an 8500, with the note that the 6510’s time depends more on temperature. These are emulator authors’ measurements, not Commodore specifications. Ordinary programs never notice, but Wolfgang Lorenz’s processor test suite checks the behaviour, and the VICE source notes that one of its tests fails if the bits fall back too quickly.
Undocumented instructions
Like the 6502, the 6510 does something for most of the opcodes its data sheet leaves out. Some combine two instructions, such as LAX, which loads A and X with the same value. A few lock the processor up. The community reference NMOS 6510 Unintended Opcodes, written by groepaz, records that they “first appeared in the context of copy protection schemes, so keeping the knowledge secret was crucial”, and that a few “unstable” ones behave differently on 6502 machines because the C64 uses the RDY line. The same document applies to the 8500.
Sources
- Commodore Semiconductor Group, 6510 Microprocessor with I/O data sheet: description (“identical to the Commodore Semiconductor Group 6502”), features (56 instructions, thirteen addressing modes, 1, 2 and 3 MHz operation, “4 MHz operation availability expected in 1986”), the three pinouts, AEC and I/O port signal descriptions, programming model.
- Commodore, Commodore 64 Programmer’s Reference Guide (1982): “Memory Management on the Commodore 64”, pp. 260–261 (the address-bus question, the port table, the direction register value of 47, CHAREN, writes under ROM); memory maps, pp. 263–265; the 6510’s I/O port and 20K of ROM.
- Sheldon Leemon, Mapping the Commodore 64 (COMPUTE! Publications, 1984), pp. 1–3: locations 0 and 1 (D6510, R6510), bits 6 and 7 “Not connected”, copying BASIC to RAM, disabling interrupts before switching out the KERNAL, copying the character ROM, GAME and EXROM.
- Commodore, C64/C64C Service Manual (March 1992, PN-314001-03): cassette circuit theory (P3–P5, motor on when P5 goes low); parts list for board assembly 250469 with the 8500.
- Christian Bauer, The MOS 6567/6569 video controller (VIC-II) and its application in the Commodore 64 (1996), section 2: the 6510’s clock rates, RDY, AEC and the BA signal.
- Marko Mäkelä, “Making stable raster routines (C64 and VIC-20)”, C=Hacking issue 10 (June 1995): crystal frequencies and dividers.
- Commodore Magazine vol. 3 no. 2 (April 1982), pp. 53–54; The TORPET issue 9 (April 1982): the 6510 announced with the Ultimax and the Commodore 64.
- VICE emulator source code,
src/c64/c64.h(web, secondary): fall-off times for bits 6 and 7 on the 6510 and 8500, and the Lorenz test suite. - groepaz, NMOS 6510 Unintended Opcodes: No More Secrets, version 1.0 (December 2025) (web, secondary): preface and scope.