Most emulators are programs: they run on an ordinary processor and imitate the old machine’s chips one after another, fast enough that the player never notices. MiSTer takes a different route. Its “cores” reconfigure a field-programmable gate array (FPGA), a chip full of logic that can be rewired, so that it behaves like the old machine’s chips at the level of their logic, all running at once. Load one core and the board is a Commodore 64; load another and it is a Neo Geo. The project began as one programmer’s answer to a tangle of video cables, and it runs on a development board sold for teaching electronics.
Fast facts
- Creator: Alexey “Sorgelig” Melnikov.
- First appeared: mid-2017, announced on GitHub in June 2017.
- Board: Terasic DE10-Nano, around $130, with an Intel (formerly Altera) Cyclone V chip that combines an FPGA with a dual-core ARM Cortex-A9 processor at 800 MHz, and 1GB of memory.
- Add-ons: an SDRAM board, needed by many cores; optional I/O board with VGA and analogue audio; USB hub, fan and cases.
- Cost: about £300 for “a decent setup”, according to Wireframe in 2022.
- Licence: open source, under the GNU General Public License.
From Minimig to MiST to MiSTer
MiSTer is the third step in a line of FPGA projects that began with the Amiga. Melnikov started thinking about it in 2015, he told Wireframe, after looking at Minimig, “an open-source re-implementation of an Amiga 500 which used an FPGA”. Next came MiST, by the engineer Till Harbaum, which recreated the Amiga and the Atari ST and put their 68000 processor inside the FPGA instead of using a separate chip. “It was how I learned about FPGA programming,” Melnikov said.
Porting cores to MiST frustrated him. “It was always a struggle to get a picture on any of my monitors or televisions, which all used HDMI,” he said. “I had to use some VGA converters, but none of them were universal, and they wouldn’t accept every possible resolution. So, while drowning in cables and switches on my table, I began to think about ways to get HDMI directly from an FPGA board.”
MiST had used a board that was expensive and hard to find. Melnikov wanted one anybody could buy, and settled on Terasic’s DE10-Nano. Because it was aimed at education, the board was subsidised by companies including ISSI, Silicon Labs and Panasonic, and sold for around $130. Its chip mixed an ARM processor with the FPGA, “a completely new beast for me”, but it was the size he wanted. In June 2017 he explained the project on GitHub: “MiSTer scales original video resolution to a standard HDMI resolution (usually 1280×720p60), so you don’t need to look for some ancient monitor with VGA input supporting non-standard resolution and frame rates.”
Making it reliable was hard. The ARM side runs Linux to handle storage and controllers, but “it doesn’t act as a normal computer requiring safe shutdown and safe reboot. MiSTer is ready for sudden reset or power off, and that was a challenge.”
What a core is
“In simple words, an FPGA is just a big array of logic elements, and you can decide how to connect them,” Melnikov told Wireframe. “There’s no CPU and no other devices. Instead, you have to create cores using elementary OR-AND logic and triggers, and this is basically how original chips were created.” A core is the description of one machine’s chips, written in a hardware description language (HDL) and loaded into the FPGA.
The difference from a software emulator is parallelism. A home computer’s processor, graphics chip and sound chip all work at the same time. A software emulator imitates them in turn, darting from one to the next as quickly as it can, so to reproduce every clock cycle it has to run “dozens, if not 100, times faster” than the original machine. In an FPGA, separate parts of the chip can be given to the processor, the graphics and the sound, and they really do run side by side. See emulation and cycle accuracy for the software side of the problem.
That makes accuracy cheaper, not automatic. A core is still somebody’s reconstruction of chips they cannot see inside. Robert Peip, who writes MiSTer cores, put it plainly: “From a pure accuracy standpoint, a software emulator can be just as good as an FPGA core. The problem comes with the speed you want to achieve.” Cores also lean on the emulator authors who went first: “Getting every bit of information out of the original console would take many years, so FPGA cores profit greatly from the research done by homebrew and emulator developers.” José Tejada said MiSTer “can potentially be as accurate as you need it to be”, and admitted that “many cores aren’t really finished. They are still in development and still being improved.”
The people writing cores
The cores are written by volunteers, often in the evenings. Tejada, known as Jotego, is a design engineer by day. “I’m spending close to 40 hours a week on the project,” he told Wireframe in 2022. “On workdays, I’ll put in maybe four hours, and at the weekends, I’ll create cores for twelve hours a day. When I have holidays, I’m probably working on MiSTer for ten hours a day.” He specialises in arcade boards; his interest began with the Yamaha YM2151 sound chip on the Ghosts ’n Goblins board, and his Capcom CPS1 and CPS2 cores brought him most of his close to 3,000 supporters on Patreon.
A core can take a week to ten days, or months. Machines that people think of as one model often changed during production, and each variation has to be handled. Peip wrote the Game Boy Advance core, which had been tested with around 1,600 official games, all of which worked, some with video glitches. In 2022 he was working on the PlayStation, which many had thought beyond the board: “I’ve already spent more time on the CD subsystem of the PlayStation than I spent on the whole WonderSwan core.” A PlayStation core is now among the project’s official repositories, its README reporting “many games working”. Core authors also add things the original hardware never had, such as save states on the NES and two linked Game Boy cores on one board for split-screen play.
By 2022 Wireframe could list the Amstrad CPC 6128, Commodore 64, ZX Spectrum, BBC Micro, SAM Coupé and PMD 85 among the computers, and the Atari 2600, Game Boy, Neo Geo and Mega Drive among the consoles, “and that’s only skimming the surface”.
Building one
Buyers can order a ready-made MiSTer from small companies that assemble them, or build their own. Wireframe’s 2022 recipe started with the DE10-Nano, “the most essential component”, then an I/O board with VGA and audio ports for anyone using a CRT, a powered USB hub, a fan and a Wi-Fi dongle. The SDRAM board matters most: the DE10-Nano’s own DDR3 memory cannot stand in for the memory many old machines used, and demanding cores such as the Neo Geo need a 128MB SDRAM module. The software is free, installed by writing an image called Mr Fusion to an 8GB microSD card. Games are loaded as ROM files, which, as Wireframe noted, leaves MiSTer in the same legal grey area as software emulation.
The commercial company Analogue uses the same Cyclone V FPGA in its own consoles, which recreate machines such as the SNES, Mega Drive and Game Boy but play original cartridges instead of ROM files.
Sources
- David Crookes, “The FPGA retro revolution”, Wireframe issue 61, March 2022, pp. 28–33: Melnikov, Tejada and Peip interviews and quotes; Minimig and MiST; the choice of the DE10-Nano, its price, processor and sponsors; the June 2017 GitHub announcement; the “Software vs hardware emulation” box; systems covered; the parts list, cost, ROMs and Mr Fusion; Analogue. Wireframe is published by Raspberry Pi Ltd.
- MiSTer project wiki, GitHub (web, secondary): the DE10-Nano’s Cyclone V SoC and ARM Cortex-A9, the SDRAM, I/O and USB hub boards, the project’s origins in MiST, and its GNU GPL licence. https://github.com/MiSTer-devel/Wiki_MiSTer/wiki
- PSX_MiSTer repository, GitHub (web, secondary): the PlayStation core and its status. https://github.com/MiSTer-devel/PSX_MiSTer