MMC3

The MMC3 is the chip that let an NES game stop partway down the screen and do something different. In January 1991 Nintendo Power explained it to its readers through Super Mario Bros. 3: “The scoreboard at the bottom of the picture is actually a second screen, which stays put even as Mario sprints from left to right. It’s made possible by a timer function that was specially built into the MMC3.”

That timer is the surprising part. The NES has no line counter a program can set, and the MMC3, sitting on the cartridge, cannot see the picture at all. It watches a single address line of the PPU and counts the pulses the PPU makes there while it fetches graphics. Nintendo made that count come out at one per scanline by telling licensees exactly where to put their tiles.

Nintendo’s own specification names the part the Multi-Memory Controller 3. Nintendo Power, writing for players, called MMCs “Memory Management Controllers”. The chip first appeared in cartridges in the last quarter of 1988, and the NESdev Wiki counts about 300 games on its boards.

Fast facts

• Maker: Nintendo; chips were manufactured by both Sharp and NEC.
• Boards: Nintendo’s TxROM family, iNES mapper 4 (two board variants are mappers 118 and 119).
• Program ROM: up to 512 KB, switched in 8 KB banks.
• Character ROM or RAM: up to 256 KB, switched as two 2 KB banks and four 1 KB banks.
• Work RAM: optional 8 KB at $6000-$7FFF, which can be battery-backed for saved games.
• Nametable mirroring: horizontal or vertical, chosen by the program.
• Interrupt: an 8-bit counter clocked by PPU address line A12, raising an IRQ when it reaches zero.
• Games: Super Mario Bros. 3, NES Play Action Football and Taito’s The Flintstones and G.I. Joe, all named in Nintendo Power; Crystalis, Wario’s Woods and Star Trek: 25th Anniversary, named in NESdev’s notes on how they use the counter.

Bank switching

Program ROM ($8000-$FFFF)

The CPU sees program ROM through four 8 KB windows. Two can be switched, using bank registers R6 and R7. The other two are fixed: $E000-$FFFF always holds the last 8 KB of the ROM, and one more window holds the second-last. Bit 6 of the value written to $8000 decides which end of the map R6 controls:

The last bank never moves because the 6502’s reset, NMI and IRQ vectors live at its top. The bank registers hold unknown values when the power comes on, so the reset code has to sit in $E000-$FFFF and set them before jumping anywhere else. R6 and R7 use only six bits, which is where the 512 KB limit comes from: 64 banks of 8 KB.

Character ROM ($0000-$1FFF in PPU space)

The PPU’s pattern tables are split into two 2 KB banks (R0 and R1) and four 1 KB banks (R2 to R5). Bit 7 of the value written to $8000 decides which half of pattern space gets the 2 KB banks:

Bank numbers always count 1 KB units, so R0 and R1 ignore their lowest bit. A 1 KB bank is 64 tiles, so a game can swap a single character’s animation frames in and out without touching the rest of its graphics.

Registers

The MMC3 sees only three CPU address lines (A0, A13 and A14) in the cartridge space, so each register answers across a whole 8 KB range: even addresses reach one register of a pair, odd addresses the other.

Every bank-select write also rewrites the two mode bits, so a program has to include its chosen modes each time. The mirroring bit does nothing on boards wired for four separate screens.

The scanline counter that does not count scanlines

NESdev’s documentation puts the mechanism in one sentence:

The MMC3 scanline counter is based entirely on PPU A12, triggered on a rising edge after the line has remained low for three falling edges of M2.

A12 is the address line that tells the PPU’s two pattern tables apart: low for $0000-$0FFF, high for $1000-$1FFF. M2 is the CPU clock. While it draws a line, the PPU fetches background tiles for most of the line and sprite patterns for a stretch near its end, and it fetches sprite patterns even when there are no sprites to draw. So if the background uses the table at $0000 and sprites use the table at $1000, A12 goes high once per line, during the sprite fetches. Filtered this way, NESdev explains, A12 stays low through all the background fetches and high through all the sprite fetches, so it rises exactly once per line.

Each counted rise does one of two things. If the counter is zero, or a reload was requested through $C001, the counter is loaded from the latch at $C000. Otherwise it goes down by one. When it is zero and the interrupt is enabled, the MMC3 pulls the CPU’s IRQ line.

Two consequences catch programmers out:

• The interval is the latch value plus one. Reaching zero takes N decrements, and reloading takes a clock of its own, so a latch of N gives an interrupt every N + 1 lines once the counter is running. A latch of 1 is the safe minimum: what a latch of 0 does depends on who made the chip.
• The counter only counts while the PPU draws. With rendering switched off there are no pattern fetches and nothing happens on A12, so the counter stops. Writing $2006 to point the PPU at $1000-$1FFF also raises A12, so code that updates video memory can clock the counter by accident.

A game that swaps the tables round, with background tiles at $1000 and sprites at $0000, still gets one rise per line, but at a different point in it, and the pre-render line can then count twice on alternate frames. NESdev gives Wario’s Woods as the example: on some resets the rightmost pixels of the bottom line of its grass flicker, because an extra count fires the interrupt a line early. In 8×16 sprite mode each sprite’s tile number chooses its own pattern table, so games using that mode have to keep every sprite in the $1000 table as well.

Programming a split

The program below draws a red screen and turns the background off partway down, so the split shows as a clean line. The NMI handler, which runs at the start of vertical blank, arms the counter for the frame; the IRQ handler acknowledges the interrupt and changes PPUMASK.

N = 99                 ; lines above the split

nmi:
    pha
    lda #$1E           ; background and sprites on
    sta $2001
    lda #0
    sta $2005          ; scroll to the top-left
    sta $2005
    lda #$88           ; NMI on; sprites from $1000, background from $0000
    sta $2000
    lda #N
    sta $C000          ; latch
    sta $C001          ; reload on the next A12 rise
    sta $E001          ; enable the interrupt
    pla
    rti

irq:
    pha
    sta $E000          ; acknowledge (this also disables it)
    lda #$16           ; background off, sprites still on
    sta $2001
    pla
    rti

The reset code, not shown, turns the NES’s own interrupt sources off before it clears the interrupt-disable flag: $40 to $4017 stops the APU frame counter’s IRQ, and 0 to $4010 stops the sample channel’s. The 6502 has one IRQ line and cannot tell who pulled it. Leave the frame counter’s IRQ on and the handler above runs at the wrong time, never clears it, and the program locks up in a storm of interrupts. The reset code also sets all eight bank registers, because they start undefined.

In the counter’s own reckoning, the reload during the pre-render line counts as its first clock. So with a latch of 99, lines 0 to 98 are drawn with the background on and the change takes effect from line 99. For a second split in the same frame, the handler writes $E000 and then $E001 again: the counter has already reloaded itself from the latch and fires N + 1 lines later. With a latch of 20 and that change, the splits land at lines 20, 41, 62 and on down the screen, 21 lines apart.

Commercial games worked the same way. NESdev notes that many update only $C000 in the handler, setting the latch one interrupt ahead, and avoid writing $C001 on consecutive lines, which can make the chip misbehave in ways that are still not fully understood. Most also toggle A12 at reset by writing $2006 repeatedly, to put the counter into a known state before the first frame.

Two makers, two behaviours

The MMC3 was made by more than one company, and the chips disagree about a latch of zero:

NESdev calls NEC’s the “alternate” or “old” behaviour and Sharp’s the “normal” or “new” one. Three revisions are known, MMC3A, MMC3B and MMC3C, with “no major behavioral differences known, except for the IRQ counter”, and MMC3B chips came from both makers. NESdev also records that “some games have been manufactured with both versions”, so two copies of one game can hold different chips. Star Trek: 25th Anniversary relies on the Sharp behaviour and glitches during its split-screen scenes on chips that lack it.

What Nintendo told licensees

Everything above can be checked against the NESdev Wiki and against real cartridges. Nintendo’s own MMC3 Specification was written for licensees and never published; a provisional draft is dated 15 December 1987 and the third edition 24 May 1988. It adds the rules Nintendo set, and some of the reasons.

The timer is a one-line clock. Nintendo describes the interval timer as clocked once per horizontal line, and its timing diagram measures that period at 63.51 microseconds. A12 is not mentioned. To a game programmer the counter was a line counter, and Nintendo’s rules kept it one.

The rules fix the pattern tables. A game using the timer had to set sprites to the upper pattern table and background to the lower one, permanently, and repeat those bits every time it wrote PPUCTRL. With 8×16 sprites, every sprite tile number had to be odd, which puts it in the upper table. The specification states the rules without explaining them; the A12 mechanism is the reason.

Blanking both layers breaks the clock. Nintendo warns that with sprites and background both switched off, the timer’s clock is undefined. Instead of blanking the screen in a scene that uses the timer, the specification tells programmers to change brightness through the palette, or to blank only one layer at a time. G.I. Joe, which turns sprites off and leaves the background on, depends on the second approach.

Acknowledging is two writes. In Nintendo’s worked example the interrupt handler writes the disable address and then the enable address, and on the last interrupt of the frame leaves the timer disabled.

The worked example and the formula disagree. The specification works a three-split frame through step by step, and both of its later latch values are the gap between interrupts minus one, matching the N + 1 interval above. The general formula printed next to them gives different values. The draft and the third edition carry the same mismatch. Nintendo’s equivalent circuit shows the underlying design: an up-counter preset with the one’s complement of the latch value, which software can treat as counting down to zero.

Nintendo’s names for the registers are its own. Bank select is the POINTER, the latch is JAM, and the reload, disable and enable addresses are P&SIT (preset and start interval timer), DITIRQ and EITIRQ. Those last three are marked as soft switches: the data written is ignored and the address alone is the command.

The specification also covers saved games. It asks for battery-backed cartridges to carry a label telling players to hold RESET while switching off, for the save to be written twice or protected by error correction, and for four addresses ($6000, $6001, $7000 and $7001) to be left out of the save area because their contents tend to be lost at power-off. Between the draft and the third edition the chip also moved from a 42-pin DIP to a 44-pin flat package.

See also

• Nintendo Entertainment System
• PPU
• MMC1
• MMC5 and MMC6
• Cartridge
• Bank switching
• Raster interrupts
• Super Mario Bros. 3