Motorola 68000 | Code Like It's 198x

In May 1979 BYTE’s news pages reported that the 16-bit processor race was under way. Zilog had been shipping samples of its Z8000 since March, Intel was cutting the price of its 8086, and “Motorola expects to start sampling their 68000 this month”. By September Motorola had a price: $249 for a single chip, with samples by the end of the year and full production in late 1980. Four years earlier MOS Technology had sold the 6502 for $25.

What the money bought was a processor that looked, to a programmer, like a much larger machine. The 68000 has sixteen 32-bit registers, a flat address space of 16 megabytes and instructions that multiply and divide. The chip underneath is narrower. Commodore’s Amiga Hardware Reference Manual puts it plainly: “internal registers are 32 bits wide, while the data bus and ALU are 16 bits.” Motorola called the part a “16-/32-Bit Microprocessor”, and the gap between those two numbers explains a good deal about programming it. Within a few years it was inside the Apple Macintosh, the Commodore Amiga, the Atari ST and, as the cut-down 68008, the Sinclair QL.

Fast facts

Maker: Motorola. Samples from 1979, $249 each.
Registers: eight data registers D0-D7 and eight address registers A0-A7, all 32 bits; a 32-bit program counter and a 16-bit status register. A7 is the stack pointer, with separate user and supervisor copies.
Buses: 16-bit data bus, 24-bit address bus, so 16 megabytes addressable.
Addressing modes: 14.
Bus cycle: four clock periods for a memory read or write.
Speed grades: Motorola’s 1993 user’s manual lists 8, 10, 12.5, 16.67 and 20 MHz parts.
Byte order: big-endian, the most significant byte at the lowest address.

Thirty-two bits, sixteen at a time

A 68000 program can add two 32-bit numbers in one instruction, and the code looks the same as for 16-bit ones: ADD.W for a word, ADD.L for a long word. The cost appears in Motorola’s timing tables. Every memory access moves sixteen bits, so a long word takes two. MOVE.W D0,(A0) takes 8 clock periods and one write. MOVE.L D0,(A0) takes 12 and two writes.

The instruction set is regular. Most instructions accept most addressing modes and most registers, so there is no equivalent of the 6502’s single accumulator or the Z80’s special-purpose register pairs. Any address register can serve as a pointer, a stack or a base for indexing, with post-increment and pre-decrement built in.

The multiply and divide instructions saved writing a routine, but they were not quick. MULU multiplies two 16-bit numbers into a 32-bit result in up to 70 clock periods, and the manual explains that the time depends on the number of 1 bits in the source. DIVU divides a 32-bit number by a 16-bit one in up to 140. On an 8 MHz machine that is up to 8.75 and 17.5 microseconds. A register shift by n bits takes 6 + 2n clock periods, so multiplying by a small power of two stayed a job for LSL.

Addressing modes

Mode	Syntax	Example
Data or address register direct	Dn, An	`MOVE.L D0,D1`
Address register indirect	(An)	`MOVE.W (A0),D0`
Post-increment	(An)+	`MOVE.B (A0)+,D0`
Pre-decrement	-(An)	`MOVE.W D0,-(A7)`
Displacement	d16(An)	`MOVE.W 4(A0),D0`
Indexed	d8(An,Xn)	`MOVE.B 0(A0,D1.W),D0`
Absolute short and long	(xxx).W, (xxx).L	`MOVE.W $4000,D0`
PC-relative	d16(PC), d8(PC,Xn)	`LEA table(PC),A0`
Immediate	#data	`MOVE.L #100,D0`

Motorola counts these as 14 modes, splitting some of the rows above.

A7 is two registers with one name

The programming model shows eight address registers, and A7 is the stack pointer. Which physical register A7 means depends on the processor’s mode. The 68000 runs either in user mode, meant for programs, or supervisor mode, meant for the operating system, and each has its own stack pointer: the user stack pointer (USP) and the supervisor stack pointer (SSP). The MC68010’s data sheet counts them separately and describes “17, 32-bit, general-purpose registers”. Later processors added more: from the 68020, Motorola’s manual splits the supervisor stack into an interrupt stack pointer and a master stack pointer.

An operating system needs to set up each program’s user stack, but in supervisor mode A7 means the supervisor stack. So the 68000 has an instruction that exists only to reach the stack pointer you are not using:

MOVE USP — Move User Stack Pointer … Operation: If Supervisor State Then USP → An or An → USP Else TRAP

The 68000’s privilege model had a gap

The clearest evidence is in the structure of Motorola’s reference manual. MOVE from SR, which copies the status register, is documented twice, in two different sections.

Under Integer Instructions, on page 4-125:

MOVE from SR — Move from the Status Register (MC68000, MC68008) Operation: SR → Destination

Under Supervisor (Privileged) Instructions, on page 6-17:

MOVE from SR — Move from the Status Register (MC68EC000, MC68010, MC68020, MC68030, MC68040, CPU32) Operation: If Supervisor State Then SR → Destination Else TRAP

The same instruction has the opposite privilege depending on the processor. On a 68000, a program in user mode can read the whole status register, including the supervisor bit and the interrupt mask. On a 68010 the same instruction traps to the operating system. The 68010 adds MOVE from CCR to its instruction list, so a user program can still read the condition codes in the low byte.

Motorola’s user’s manual promises that “any user-mode programs using the MC68000 instruction set will run unchanged” on the later processors. A 68000 program that reads SR in user mode is the exception.

What the 68010 added

Motorola’s family list describes each part in a few words:

Part	Motorola’s description
MC68000	“16-/32-Bit Microprocessor”
MC68008	“16-Bit Microprocessor with 8-Bit Data Bus”
MC68010	“16-/32-Bit Virtual Memory Microprocessor”
MC68020	“32-Bit Virtual Memory Microprocessor”
MC68851	“Paged Memory Management Unit”

The 68010 fits the same socket as the 68000. What it adds is the ability to recover from a bus error, and the difference shows in what each processor saves when one happens.

When a 68000 takes a bus or address error, it pushes seven words: the address it was trying to reach, a word saying whether it was reading or writing and what kind of access it was, the instruction register, the status register and the program counter. That is enough to report what went wrong. It is not enough to finish the instruction, because the processor’s internal state is lost.

The 68010’s frame for the same error, Format $8, is 29 words long. After the status register, program counter and vector offset come a special status word, the fault address, the data and instruction buffers and “INTERNAL INFORMATION, 16 WORDS”. Motorola’s technical summary for the 68010 explains the purpose: “When an address error or bus error is encountered, the MC68010 will place its internal state on the supervisor stack”, and when the handler finishes, the processor reloads that state “and resume[s] execution”. That is what virtual memory needs. The handler can load the missing page from disk and let the interrupted instruction carry on.

The rest of the family

68008: the 68000’s instruction set on an 8-bit data bus, made to cut the cost of the memory and support chips around it. The 48-pin version has 20 address lines and reaches 1 megabyte; the 52-pin version has 22 and reaches 4. Sinclair used the 48-pin part in the QL. Sinclair’s service manual calls it “a 32-bit microprocessor with an 8-bit data bus”, and the Sinclair QL entry covers why it chose it.
68010: pin-compatible with the 68000, with the recoverable bus errors described above, a vector base register that lets the exception table move out of low memory, and a loop mode for short DBcc loops.
68020: the first fully 32-bit member. Its manual describes “a nonmultiplexed bus with 32 bits of address and 32 bits of data”, an on-chip instruction cache and an interface for the 68881 and 68882 floating-point coprocessors. Later Amigas used the 68020, 68030 and 68040.

The machines

Machine	Processor and clock	Source
Apple Macintosh (1984)	68000 at 7.8336 MHz	Apple, Inside Macintosh: Hardware
Sinclair QL (1984)	68008 at 7.5 MHz	Sinclair, QL Service Manual
Commodore Amiga (1985)	68000 at 7.09379 MHz (PAL) or 7.15909 MHz (NTSC)	Amiga Hardware Reference Manual
Atari ST (1985)	68000 at 8 MHz	Atari ST Internals
Sega Mega Drive	68000 at 7.67 MHz (NTSC) or 7.60 MHz (PAL)	Sega, Genesis Software Manual
Neo Geo	68000 as the main processor	SNK, Neo-Geo hardware specification
HP 9000 Series 200	68000 at 8 MHz	Hewlett-Packard, Series 300 technical data

The clocks tell a story about each design. The Amiga’s is a quarter of the master crystal that also times the display, so one low-resolution pixel lasts exactly one processor clock. Atari ST Internals says the ST’s 8 MHz “was chosen as a ‘middle of the road’ frequency”. Sega’s own manual shows how loosely the figure was quoted: its overview page gives “68000 @8mHz”, while the register that reports the console’s configuration gives 7.67 MHz for NTSC machines and 7.60 MHz for PAL ones.

The Amiga also shows where the 68000 met a system it was not designed for. Its custom chips share memory with the processor and take turns on the bus, and the Hardware Reference Manual warns that the 68000’s test-and-set instruction “should never be used in the Amiga; the indivisible read-modify-write cycle that is used only in this instruction will not fit into a DMA memory access slot.”

By the 1990s the 68000 was one of the skills British recruitment advertisements asked for by name. Edge’s recruitment pages in April 1994 carried calls for “68000/65C816 PROGRAMMERS” and for “Programmers with Z80, 6502, 68000, 65816 experience”, the processors of the Mega Drive, the Super Nintendo and the machines before them.

Sources

BYTE, May 1979, p. 118, and September 1979, p. 116: BYTE News reports on the 68000’s sampling, the $249 single-unit price and the production schedule, alongside the Z8000 and the 8086.
Motorola, M68000 8-/16-/32-Bit Microprocessors User’s Manual, ninth edition (1993): the family overview, 32-bit registers, 16-bit data and 24-bit address buses, 16-Mbyte range and 14 addressing modes (pp. 1-1 to 1-3, 2-1); the 68008’s 48-pin and 52-pin versions (p. 1-2); the four-clock bus cycle; the speed grades (section 10); instruction timings for MOVE, the shifts, MULU, MULS, DIVU and DIVS (section 8).
Motorola, M68000 Family Programmer’s Reference Manual (1992): the part descriptions (p. 1-1); the system stack and the USP, ISP and MSP (§1, §2.6.1); MOVE from SR as an integer instruction (p. 4-125) and as a privileged one (p. 6-17); MOVE USP; Appendix A’s note that MOVE from SR “is not privileged for the MC68000 and MC68008”; the exception stack frames (Appendix B, pp. B-3 to B-6).
Motorola, MC68010 16-/32-Bit Virtual Memory Microprocessor, technical summary: 17 32-bit registers, pin compatibility with the 68000, MOVE from CCR, virtual memory and machine concepts, instruction continuation, loop mode.
Motorola, MC68020 32-Bit Microprocessor User’s Manual, first edition (1992), section 1: the 32-bit address and data buses, instruction cache and coprocessor interface.
Commodore-Amiga, Amiga Hardware Reference Manual, third edition (Addison-Wesley, 1991): the 68000’s 16-bit data bus and ALU and its clock speeds (p. 2); the TAS warning (p. 196).
Apple Computer, Inside Macintosh: Hardware (draft, February 1985): the MC68000 “clocked at 7.8336 megahertz”.
Sinclair Research, Sinclair QL Service Manual, issue 3, October 1985, section 1: the MC68008 and its 7.5 MHz clock from the ZX8301.
Atari ST Internals (Abacus Software, 1986), p. 11: the ST’s 8 MHz clock.
Sega, Genesis Software Manual (1990): the technical overview, “68000 @8mHz”; the version register at $A10001, “NTSC CPU clock 7.67 MHz”, “PAL CPU clock 7.60 MHz”.
SNK, Neo-Geo hardware specification (1989): the 68000 as the main CPU.
Hewlett-Packard, HP 9000 Series 300 Technical Data (1986): the Series 200’s 8 MHz MC68000.
Edge issue 7, April 1994: recruitment advertisements for 68000 and 65816 programmers.