In August 1976 BYTE told its readers about a new processor from “a fairly new company in Los Altos”. Zilog had been sampling the Z80 “since early this year”, and it ran every one of the 78 instructions of Intel’s popular 8080 as a subset of its own 158. It was also expensive. A single sample cost $200, and even at 25 to 99 units it was $80 each, “still more expensive … than either the 8080A, 6800 or 6502”. BYTE’s case for it was that the chip needed so little support circuitry that “when the cost of all the support devices the 8080A requires are included, the costs are comparable.”
That argument won. The Z80 went into the TRS-80, Sinclair’s ZX81 and Spectrum, the Amstrad CPC, every MSX computer and the ColecoVision, and it later worked as the sound processor inside Sega’s Mega Drive. For British children teaching themselves machine code on a Spectrum or a CPC, the instruction set they learnt was the Z80’s.
Who made it
Zilog was founded by engineers from Intel. A 1980 guide to the TRS-80 calls Federico Faggin the “creator of the 8008, 8080, and Z-80 microprocessors” and “founder and President of Zilog”. The Home Computer Advanced Course, a British partwork of the mid-1980s, credits the Z80 to Faggin and Masatoshi Shima, “two employees of the microchip manufacturer Intel”, who had worked on the 8080. They “decided to design the new chip to be compatible with the 8080”, so it could run the software already written for it. By then, the partwork said, Zilog was still making “around a million a month”.
What made it easy to build with
The 8080 needed three supply voltages, +12, +5 and −5 V, a two-phase high-voltage clock and a separate system controller chip. BYTE listed the Z80’s answers. It ran from a single +5 V supply and a single-phase clock, and it produced its own memory and I/O control signals.
It also refreshed dynamic memory by itself. Dynamic RAM loses its contents unless every row is read again at regular intervals. The Z80 does this in time that would otherwise be wasted:
The time during T3 and T4, when the Z80 decodes the instruction internally and the address bus would otherwise be idle, is used in Z80-based systems for refreshing the dynamic memories. This process is called transparent refresh.
The refresh address comes from the R register. Zilog’s manual says that seven of its eight bits “are automatically incremented after each instruction fetch”, while the eighth “remains as programmed”. The upper half of the refresh address comes from the I register: “During refresh, the contents of the I Register are placed on the upper eight bits of the address bus.”
Sinclair’s machines put both registers to uses Zilog had not planned:
- The ZX81 draws its display with them. The ZX81 has no video chip. During the display, its ULA reads the character patterns from the address formed as
I*256 + CODE*8 + COUNT, with I initialised to1Ehex so that it points at the character set in the top of the ROM. - On the Spectrum, I decides whether the screen snows. The Spectrum’s ULA does not treat a refresh address in the range
$4000–$7FFFas a clash with its own video fetches, but the memory circuits still see an access to the lower 16K of RAM. The two collide and the picture breaks up into “snow”. A program that sets I to a value from$40to$7F, for example to point interrupt mode 2 at a table in that memory, puts every refresh cycle into that range.
The registers
Zilog’s manual counts 208 bits of registers visible to the programmer:
| Registers | Purpose |
|---|---|
| A, F | Accumulator and flags |
| B, C, D, E, H, L | General-purpose 8-bit registers, also used in pairs as BC, DE and HL |
| A’, F’, B’, C’, D’, E’, H’, L’ | The alternate set, swapped in by EX AF,AF' and EXX |
| IX, IY | 16-bit index registers, used with a signed 8-bit offset: (IX+d) |
| SP, PC | Stack pointer and program counter |
| I | High byte of the interrupt table address in interrupt mode 2; also the high byte of the refresh address |
| R | Refresh counter: bits 0–6 count, bit 7 holds whatever was loaded |
EXX swaps BC, DE and HL with their alternates in one byte and 4 T-states, and changes no flags. Zilog meant the alternate set for fast interrupt handling: “one set of general-purpose registers and an Accumulator/Flag Register can be reserved for handling this fast routine.” Software did not always use it that way. The Spectrum’s own ROM uses the alternate registers inside its floating-point calculator. Its 50 Hz interrupt routine does not use EXX at all. It pushes AF, HL, BC and DE onto the stack, updates the frame counter and scans the keyboard.
Halting is not stopping
HALT does not stop the processor. In Zilog’s words, “During HALT, the CPU executes NOPs to maintain memory refreshes.” A halted Z80 keeps fetching instructions it throws away, so that R keeps counting and the dynamic RAM keeps its contents. It stays in this loop until an interrupt or a reset arrives.
On the Spectrum this makes HALT the standard way to wait for the next frame. The ULA interrupts the Z80 once per television frame, and the ROM’s interrupt routine counts frames “every 20 ms”. A game loop that executes HALT resumes at the start of the next frame.
Instructions that shaped the code
| Instruction | What it does |
|---|---|
LDIR, LDDR |
Copy BC bytes from (HL) to (DE), repeating by themselves: 21 T-states per byte, 16 for the last. With BC set to 0 the copy runs through all 64K. |
DJNZ e |
Decrement B and jump if it is not zero: a loop counter in one 2-byte instruction, 13 T-states when it jumps and 8 when it does not. No flags change. |
JR e |
Relative jump with a signed 8-bit offset, two bytes long |
BIT, SET, RES |
Test, set or clear any bit of a register or memory byte |
DAA |
Adjust A after addition or subtraction in binary-coded decimal, for scores and counters |
IN A,(n), IN r,(C) |
Read an I/O port. IN A,(n) puts A on the top half of the address bus, so a port address has 16 bits, not 8. |
The Spectrum reads its keyboard with those 16-bit port addresses. All eight half-rows of keys answer on port 254, and the high byte of the address picks which half-row: IN 65278 reads CAPS SHIFT to V, IN 32766 reads SPACE to B.
The Z80 has three interrupt modes. Mode 0 behaves like the 8080. Mode 1 always calls address $0038, which is the mode the Spectrum’s ROM uses. Mode 2 builds the handler’s address from I and a byte supplied by the interrupting device. The non-maskable interrupt always goes to $0066, which is the address that freezer cartridges such as the Multiface rely on.
Undocumented instructions
Zilog’s manual leaves out a set of instructions that the silicon executes anyway. Sean Young’s The Undocumented Z80 Documented lists them:
- Half index registers. A
DDorFDprefix turns an instruction that uses H or L into one that uses the high or low byte of IX or IY, soLD IXh,Aworks. The exception is an instruction that already uses(IX+d):LD H,(IX+d)still loads the real H. SLL. A shift left that sets bit 0 instead of clearing it, unlikeSLA.OUT (C),0. Sends zero to the port in BC.- Two hidden flags. Bits 5 and 3 of F are copies of bits 5 and 3 of a result. A program can only see them by pushing AF and reading it back.
Where it went
| Machine | Z80 clock |
|---|---|
| ZX81 | 3.25 MHz |
| ZX Spectrum 16K and 48K | 3.5 MHz |
| Spectrum +2 and +3 | 3.5469 MHz |
| Amstrad CPC | 4.00 MHz |
| MSX | 3.579545 MHz, the NTSC colour subcarrier |
| Sega Mega Drive | 4 MHz, as the sound processor |
The TRS-80, the ColecoVision and Sega’s Master System also used it. The first Z80 was rated at 2.5 MHz. Zilog’s current manual lists parts from 6 to 20 MHz.
Sources
- Burt Hashizume, “Microprocessor Update: Zilog Z80”, BYTE, August 1976, pp. 34–38: sampling since early 1976; 158 instructions including the 8080A’s 78; single +5 V supply and single-phase clock; 2.5 MHz maximum; built-in refresh; interrupt modes and the NMI at 0066 hex; prices against the 8080A, 6800 and 6502.
- Zilog, Z80 CPU User Manual (UM008011-0816), pp. 1–3 (register set, I and R registers, the alternate set, speed range), p. 7 (HALT pin), the interrupt response section (mode 1 at 0038h, NMI at 0066h), p. 126 (EXX), p. 132 (LDIR), p. 173 (DAA), p. 181 (HALT), pp. 278–279 (DJNZ), p. 295 (IN A,(n)).
- Ramesh Gaonkar, The Z80 Microprocessor: Architecture, Interfacing, Programming, and Design (Macmillan, 1988), p. 491: transparent refresh.
- Robert M. Richardson, Disassembled Handbook for TRS-80, volume 2 (Richcraft Engineering, 1980), introduction: Faggin as creator of the 8008, 8080 and Z-80 and president of Zilog.
- The Home Computer Advanced Course issue 11 (Orbis), p. 220: Faggin and Shima, 8080 compatibility, production of around a million a month.
- Chris Smith, The ZX Spectrum ULA: How to Design a Microcomputer (ZX Design and Media, 2010), p. 24 (the 8080 developed by Faggin at Intel; Z80 binary compatible with it) and chapter 23 (the snow effect).
- Don Thomasson, The Ins and Outs of the TS1000 & ZX81 (Melbourne House, 1983), pp. 35–36 and 47: the ZX81 display and the I register; the 3.25 MHz clock.
- Ian Logan and Frank O’Hara, The Complete Spectrum ROM Disassembly (Melbourne House, 1983): the interrupt routine at 0038 hex, the frame counter “every 20 ms”, the 3.5 MHz clock and the calculator’s use of the alternate registers.
- ZX Spectrum +3 Service Manual (Amstrad): “Z80A running at 3.54690MHz”.
- Sinclair ZX Spectrum +2 manual (Amstrad), Part 23, pp. 138–139: the keyboard half-row port addresses, “254+256*(255-2↑n)”.
- CPC464 Firmware (AMSOFT, 1984), appendix 12: “a Z80A running at a clock frequency of 4.00 MHz”.
- MSX Technical Data Book (ASCII Corporation, 1984), section 1.3: “Z80A compatible, Clock 3.579545MHz”.
- Sega Genesis Software Manual (Sega, 1990): “Z80 @4mHz”, controlling the sound chips.
- ColecoVision Technical Manual (Coleco, 1982): the Z-80A CPU.
- TRS-80 Micro Computer Technical Reference Handbook (Radio Shack, 1978): the Z80 processor circuit.
- Sean Young, The Undocumented Z80 Documented, version 0.91 (2005), chapters 2 and 3 (modern reference): undocumented opcodes and flags; the 8080 instructions run “in almost the same way”.
- Sega Master System Compendium (modern book): the Master System’s Z80.