MMC1

In Japan, The Legend of Zelda and Metroid were Famicom Disk System games. The disks held more than the cartridges of the day and could save a game. To sell them in the West, Nintendo needed a cartridge that could do the same, and the MMC1 was the chip that made one. Nintendo Power told its readers in January 1991 that “the first MMC chip to be used for the NES is still the most popular today”, and that games “like The Legend of Zelda and Metroid became possible only after the MMC1 was developed”.

The MMC1 gives a cartridge up to 256 KB of program ROM and 128 KB of graphics, switched in banks, lets the program choose how the nametables are mirrored, and connects 8 KB of RAM that a battery can keep alive. It is also the oddest mapper to program. To keep its pin count down, it takes its data one bit per write, so setting any register takes five stores.

Nintendo’s own specification calls the part simply the MMC, short for Multi Memory Controller. The name MMC1 appears in Nintendo’s paperwork only in 1989, once later controllers existed. Nintendo Power, writing for players, called MMCs “Memory Management Controllers”, as the MMC3 entry records.

Fast facts

• Maker: Nintendo. NESdev records the first chips as made by ROHM, with a change to the MMC1A, probably made by Ricoh, around the 39th week of 1988.
• Package: 24-pin shrink DIP.
• Boards: Nintendo’s SxROM family, including SNROM, SKROM, SLROM and SGROM; iNES mapper 1. NESdev’s infobox counts about 390 games.
• Program ROM: up to 256 KB, switched as one 16 KB bank beside a fixed one, or as a 32 KB bank. The SUROM and SXROM boards reach 512 KB by borrowing a graphics bank line.
• Graphics ROM or RAM: up to 128 KB, switched as two 4 KB banks or one 8 KB bank.
• Work RAM: 8 KB at $6000-$7FFF, optionally battery-backed. Some boards, most of them Japanese, carry 16 KB or 32 KB.
• Mirroring: vertical, horizontal, or one screen, chosen by the program.
• No interrupt. The chip has no IRQ pin, so a split screen needs the PPU’s sprite 0 hit or a timed loop.
• Games: The Legend of Zelda, Metroid and Kid Icarus on SNROM boards; Castlevania II: Simon’s Quest on SLROM; Mega Man 2 on SGROM; Ocean’s Darkman, whose Nintendo Power data box in August 1991 lists its memory as “MMC1”.

Configured one bit at a time

Most mappers take a bank number in a single write. The MMC1 sees only two bits of the CPU’s data bus. Bit 7 clears its shift register. Bit 0 carries one bit of data. NESdev gives the reason in a sentence: “the MMC1 is configured through a serial port in order to reduce its pin count”.

A write anywhere in $8000-$FFFF with bit 7 clear shifts bit 0 into a 5-bit shift register, lowest bit first. On the fifth write the chip copies the five bits into one of four internal registers and empties the shift register ready for the next value. Only the fifth write’s address matters, and only its top two bits below A15 (A14 and A13), because those are the only address lines the chip has. They pick the register:

This routine, the same shape as the one in NESdev’s MMC1 page, loads the program bank register from the accumulator:

; A = bank number (bits 0-4)
set_prg_bank:
    sta $E000      ; bit 0
    lsr a
    sta $E000      ; bit 1
    lsr a
    sta $E000      ; bit 2
    lsr a
    sta $E000      ; bit 3
    lsr a
    sta $E000      ; bit 4: the fifth write loads the PRG bank register
    rts

Nintendo’s specification gives licensees an almost identical routine and recommends one address per register: $9FFF, $BFFF, $DFFF and $FFFF, the top of each window. Any address in the right window works, but those four turn up throughout MMC1 game code.

Writing into ROM space causes no clash on the data bus. Nintendo’s specification explains that the MMC combines the ROM’s select signal with the CPU’s read/write line inside the chip, so the ROM does not drive the bus during a write.

Resetting, and the trouble with interrupts

Any write with bit 7 set empties the shift register and also sets the control register’s program mode to 3, which fixes the last bank at $C000. A reset routine can do that with one store, and a program that has lost count of its five writes can start again.

The five writes are a hazard if an interrupt lands between them. An NMI handler that switches banks part-way through the main program’s sequence leaves the chip holding a half-built value, and the main program’s remaining writes then finish the wrong number. NESdev’s programming notes describe two ways round it: have the handler reset the chip and set a flag so the main program retries, or have the main program save the bank number and reset the chip before every switch, so that the handler can put the right bank back.

One more trap catches emulators and clever code. NESdev reports that when the chip is written on consecutive CPU cycles it ignores every write after the first, except a bit-7 reset. Read-modify-write instructions such as INC do exactly that, writing the old value and then the new one. Nintendo’s own reset routine uses an INC on a ROM byte with bit 7 already set, so both writes are resets whatever happens to the second. Bill & Ted’s Excellent Adventure does it on a byte holding $FF, and relies on the chip ignoring the $00 that follows.

Registers

Control ($8000-$9FFF)

Mode 3 is the usual one, and the one a reset selects: the 16 KB bank at $C000 holds the interrupt vectors and the main program, and the program swaps other 16 KB banks in below it. Software-controlled mirroring mattered to Metroid, which scrolls both sideways and up and down. Nintendo Power singled that out: “much of the challenge and excitement comes from the ability of the game to scroll both horizontally and vertically.”

CHR bank 0 and 1 ($A000-$BFFF, $C000-$DFFF)

Each holds a 5-bit bank number, enough for 32 banks of 4 KB. In 8 KB mode, bank 0 alone selects the whole pattern-table space and its lowest bit is ignored. Boards with only 8 KB of graphics RAM have spare lines here, and some reuse them: SNROM uses the top bit as an extra enable for the work RAM, and SOROM, SUROM and SXROM use them to bank extra RAM or to choose which 256 KB half of a 512 KB program ROM is in view.

PRG bank ($E000-$FFFF)

Bits 0-3 choose a 16 KB bank; in 32 KB mode the lowest bit is ignored. Bit 4 is the one bit Nintendo redefined (see below).

What Nintendo told licensees

Nintendo’s MMC Cassette Programming Specification was written for cartridge developers and never published. The first issue is dated 18 November 1986 and the revision 26 March 1987. Everything above can be checked against the NESdev Wiki; the specification adds Nintendo’s rules and reasons.

Copy protection was part of the pitch. The specification lists five features of the MMC. Four are about capacity, bank sizes, battery backup and screen control. The fifth is that it is effective against copying, because a dedicated chip is hard to replace with ordinary logic.

Every 16 KB bank had to be able to start the machine. No reset signal reaches a Famicom cartridge, so the MMC cannot know its own state at power-on, and the bank at $C000 when the CPU fetches its reset vector is undefined. Nintendo therefore required vectors and an initialisation routine in every 16 KB bank of program ROM. NESdev adds that later tests found the chip usually, though not reliably, powers up in mode 3, and that several commercial games carry reset code only every 32 KB.

Boards had names from the start. The 1987 revision lists the permitted cartridge configurations by board name: SNROM with 8 KB of graphics RAM, SKROM with 128 KB of graphics ROM, and SLROM, in versions with and without 8 KB of work RAM and a CR2032 battery. Nintendo’s list gives SLROM battery-backed graphics RAM, which is not what the boards that shipped under that name carry, so the list shows what was planned in 1987 rather than what was made.

The MMC1B revision

A Nintendo notice dated 15 June 1989 introduced the MMC1B to replace the MMC1A, to improve how well it kept RAM data. Licensees were asked to program for the new part from then on, starting with games that needed battery backup.

The change is in bit 4 of the PRG bank register. On the MMC1B it controls access to the work RAM: 0 allows access and 1 blocks it. Nintendo’s notice tells programmers that the bit is normally set at power-on, so they must clear it before using the RAM. A save kept behind a closed gate is safer from stray writes while the console’s power is falling. NESdev describes the RAM as enabled by default, so a program that follows Nintendo’s instruction works either way.

On the MMC1A the same bit did something else: it made bit 3 drive the top program-ROM address line directly, a feature meant for a board with two 8 KB banks of RAM. NESdev notes that no such board was produced, and that two known games write to that bit and still expect their RAM to work, which they do only on an MMC1A. An emulator therefore has to know which revision a cartridge carries.

Why it mattered

Before the MMC1, a cartridge like Super Mario Bros. had 32 KB of program and 8 KB of graphics, fixed mirroring and nothing to save to. The MMC1 multiplied the program space by eight and made mirroring and saving part of the cartridge. Nintendo Power’s 1991 guide to Game Paks explained why saving mattered: before it, a player who wanted to finish a game “had to do it during one play session”. Zelda kept three saved games on its battery-backed RAM. Metroid’s cartridge used the MMC1 for its scrolling but, with no battery, gave the player a password instead.

Its successors took different routes. The MMC3 arrived in late 1988 with registers written a byte at a time, finer banks and a scanline counter, and the MMC5 went further still. Nintendo was still revising the MMC1 in 1989, and Nintendo Power could call it the most popular MMC in 1991.

See also

• Nintendo Entertainment System
• PPU
• MMC3
• MMC5
• VRC2
• Famicom Disk System
• Bank switching
• Copy protection
• Nintendo
• The Legend of Zelda
• Metroid