MOS 6502 | Code Like It's 198x

In November 1975 BYTE told its readers that it had been wrong about the price of computing. “We thought that the ‘age of the affordable computer’ had arrived when you could buy a microprocessor chip for $150,” it wrote. Now a calculator-chip maker in Norristown, Pennsylvania, MOS Technology, was offering one for $20, and for $25 you could have a version with its own clock circuit: the MCS6502.

The 6502 is a small processor. It has one accumulator where Motorola’s 6800 had two, and no instructions that work on 16-bit numbers. What it has instead is quick access to the first 256 bytes of memory, which its programmers used as a bank of extra registers. That design, and that price, put it inside the Apple II, the Commodore PET, the Atari 2600 and 8-bit computers, the BBC Micro and the VIC-20. Two variants, the 6510 and Ricoh’s 2A03, ran the Commodore 64 and the Nintendo Entertainment System.

Fast facts

Designers: a team led by Chuck Peddle, with Bill Mensch as lead designer and several engineers from Motorola’s 6800 project.
Launch: WESCON, San Francisco, 16-19 September 1975, at $25. The MCS6501, with the same instructions but the 6800’s pinout and no on-chip clock, was $20.
Registers: accumulator A, index registers X and Y, stack pointer S and status register P, all 8 bits, plus a 16-bit program counter.
Instructions: 56 instructions and 13 addressing modes, giving 151 opcodes.
Address space: 64K, over 16 address lines. The data bus is 8 bits.
Clock: MOS’s data sheet gives timings for 1 MHz parts and 2 MHz “A” parts.
Zero page: addresses $0000-$00FF, reached with one-byte addresses.
Stack: always in page one, $0100-$01FF, growing downwards.
Second sources: Apple’s 1979 reference manual lists MOS Technology, Synertek and Rockwell as makers.

Peddle, Mensch and the Motorola lawsuit

Chuck Peddle joined Motorola in 1973 to work on the 6800. BYTE credited him in 1982 with “the architecture for all the peripheral chips of the 6800 and all the I/O (input/output) structure”. Selling the 6800 to companies such as Ford and Hewlett-Packard, he kept hearing the same complaint about its $300 price, according to Tim Danton’s history. He began work on a cheaper processor. Motorola sent him “a formal letter … saying you have to stop work on your low-cost microprocessor”, he told the Computer History Museum in 2014.

MOS Technology’s president, John Paivinen, offered him a team of his own. In 1974 Peddle left Motorola and took several of the 6800’s engineers with him, among them Bill Mensch. BYTE called Peddle the “chief architect” of the 6502. Mensch, in the words of the 1986 book Programming the 65816, was “the lead designer on the original 6502 development project”.

MOS made two processors with the same instructions. The 6501 plugged into a 6800’s socket. The 6502 had a different pin arrangement and its own clock generator, which BYTE thought made it “probably cheaper in original design”. Motorola sued Peddle’s team. Danton records Peddle’s insistence that the chip took nothing from the 6800 and that he had told his engineers to leave their paperwork behind. One of them did not, which added weight to Motorola’s case.

WESCON, 1975

BYTE went to press in late August 1975 with the chip still “just a promise”. It expected it on sale at the Western Electronic Show and Convention (WESCON) in San Francisco, 16-19 September. Danton describes what happened there: the organisers banned sales on the show floor, so buyers crowded into a MOS hotel suite nearby to pay their $25. Peddle said later that two of the visitors were Steve Wozniak and Steve Jobs, who went home with a processor and its manuals.

BYTE’s comparison with the 6800 found the new chip quicker at the same clock. A store to an absolute address took 4 cycles against the 6800’s 5, a subroutine call 6 against 9, and a branch not taken 2 against 4. The company, BYTE added, “has hinted broadly that the chip can be run at … 2 or even 3 MHz”.

The first chips were missing an instruction. MOS’s programming manual of January 1976 lists ROR, rotate right, as “Available on Microprocessors after June, 1976”. Programs written for the first chips had to do without it.

Why zero page is fast

Zero page is usually explained as “one byte shorter”. MOS’s own manual explains it as one cycle shorter, and says where the cycle goes.

An absolute access needs three bytes and four cycles: opcode, address low, address high, data. A zero-page access needs two bytes and three cycles, because the processor works out what kind of instruction it is holding before it has finished reading the operand:

by the end of the second cycle, the microprocessor has decoded the fact that this is a zero page operation and on the next cycle, it outputs address 00, as the effective address high, along with the address low that it just fetched

The high byte is never fetched because the processor already knows it is zero. A quarter of the cycles are saved, for the price of keeping your variables in the first 256 bytes, and MOS says this is how the chip is meant to be used: “the user should organize his memory so that he is keeping his most frequently accessed RAM values in the memory locations between 0 and 255”.

With only three working registers, 6502 programmers treated zero page as the rest of their register file. It is also the only place a pointer can live: the indirect modes (zp,X) and (zp),Y read their 16-bit address from a pair of zero-page bytes. On a home computer that meant sharing the space with the operating system. On the Commodore 64, Mapping the 64 sets aside just four locations, 251 to 254, as “Four Free Bytes of Zero Page for User Programs”, the only ones BASIC is guaranteed not to alter. Other locations can be borrowed “on a noninterference basis”.

Where the cycle comes back

The saving is not uniform, and the manual says so:

there is no time savings of Zero Page indexing over absolute indexing without page crossing … In the case of the Zero Page, there is no opportunity for this type of overlap; therefore, indexed Zero Page instructions take one cycle longer than non-indexed instructions.

An absolute indexed access fetches the address high byte in the same cycle as it adds the index to the low byte. Zero page has no high byte to fetch, so there is nothing to overlap with, and the addition costs a cycle of its own. LDA $40,X takes four cycles, the same as LDA $4000,X.

Zero-page indexing also never leaves zero page. The manual states that “00 is forced into address high under all circumstances”, and its worked example adds an index of $10 to $F7 to reach $0007, not $0107.

The read that goes to the wrong address

When an absolute indexed access crosses a page boundary, the processor adds the index to the low byte first and puts that address on the bus before the carry has reached the high byte. For one cycle it is looking at the wrong page:

In both Zero Page indexed and absolute indexed with a page crossing, there are incorrect addresses calculated. Provisions have been made to make certain that, only a READ operation occurs during this time. Memory modifying operations such as STORE, SHIFT, ROTATE, etc. have all been delayed until the correct address is available, thereby prohibiting any possibility of writing data in an incorrect location and destroying the previous data in that location.

MOS knew the address would be wrong for a cycle, and guaranteed only that nothing would be written there. The cost shows in the timing tables. A read such as LDA $4000,X takes four cycles, and the manual’s appendix marks it “Add 1 if page boundary is crossed”. A store, STA $4000,X, always takes five, and a read-modify-write such as ROR $4000,X always seven, because they always wait for the corrected address.

For ordinary memory the stray read costs nothing but time. For memory-mapped hardware it can matter, because reading a chip’s register can clear a flag or acknowledge an interrupt. Programming the 65816 lists the extra read as “a possible cause of interference with memory-mapped I/O devices on the 6502”, and the CMOS 65C02 removed it.

The stack is next door to zero page

The processor puts 01 on the top eight address lines for every stack operation, the way it puts 00 there for zero page. The manual explains the choice: page one “would be the next memory location added if the Zero Page operation requirements exceed Page Zero memory capacity”. An 8-bit stack pointer with a fixed 01 above it is why the 6502 stack holds 256 bytes and cannot be moved.

A system with only a few hundred bytes of RAM could still have a stack. MOS suggested wiring the memory so that address line 8 was ignored, which makes page one a mirror of page zero: “the user can either locate the stack in Page Zero or Page One, depending on whether or not Page One exists for his hardware”.

Status register (P)

Bit	Flag	Meaning
7	N	Negative: a copy of bit 7 of the result
6	V	Overflow: signed overflow from ADC or SBC
5		No effect; always 1 in the copy pushed to the stack
4	B	Break: 1 in the copy pushed by BRK or PHP, 0 when pushed by IRQ or NMI
3	D	Decimal: ADC and SBC work in binary-coded decimal
2	I	Interrupt disable: when 1, IRQ is ignored
1	Z	Zero: the result was 0
0	C	Carry: out of an addition, a shift or a comparison

MOS’s data sheet labels bit 4 the “BRK command” flag. The NESdev community’s analysis of the chip adds that it is not stored in the processor at all: “there are only six flags in the processor status register within the CPU”, and B and bit 5 exist only in the byte pushed to the stack. That is how an interrupt handler tells a BRK from a hardware interrupt, since both use the vector at $FFFE.

Interrupts and reset

The 6502 has three entry points, each a 16-bit vector at the top of memory: NMI at $FFFA, reset at $FFFC, and IRQ and BRK sharing $FFFE. IRQ is a level input: the manual says the line “senses it needs service when it remains low”, and the processor answers it after the current instruction if the I flag is clear. NMI is “edge sensitive”, triggered when the line goes from high to low, and it is taken “no matter what the status of the interrupt disable”. The interrupt sequence itself takes seven cycles, and the manual puts the longest wait from an NMI to its handler at fourteen.

Reset does almost nothing for you. The manual’s list of “automatic operations of the microprocessor during reset” is two items: set the interrupt disable bit and jump through the reset vector. It tells the programmer to set up the stack at once with LDX and TXS. The decimal flag is not cleared, and Programming the 65816 lists its state after reset as unknown, which is why 6502 start-up code also begins with CLD.

Quirks

JMP indirect across a page boundary. JMP ($20FF) should take its target from $20FF and $2100. The manual’s own cycle-by-cycle example shows why it does not: the processor fetches the low byte, then does “Add 1 to IAL”, the low byte of the pointer only. The high byte of the target comes from $2000. The 65C02 fixes it at the cost of a cycle.
Decimal mode flags. In decimal mode ADC and SBC produce correct BCD results, but Programming the 65816 warns that “the negative, overflow, and zero flags in the status register are not valid”. The 65C02 makes them valid, again at the cost of a cycle.
Page-crossing penalties. Covered above: one extra cycle for an indexed read that crosses a page, none for a store or read-modify-write, which always pays the maximum.

Undocumented opcodes

The 6502 decodes 151 of its 256 opcodes. The other 105 were left undefined, and MOS never documented what they did. Programming the 65816 describes the results as “unpredictable” and says they “can include causing the processor to ‘hang’”.

Programmers found out anyway. groepaz’s reference No More Secrets records that these “illegal” opcodes “first appeared in the context of copy protection schemes, so keeping the knowledge secret was crucial”. Most of them turn out to be stable and to combine two ordinary operations: LAX loads A and X at once, SAX stores A AND X, and DCP decrements memory and then compares it with A. A handful are “unstable”, and some lock the processor up. The same document traces one of the unstable ones, LAX #imm, through the code of Wizball, and lists the chip-dependent constants that would have crashed the game.

The 65C02 turned every unused opcode into a no-operation, so code that uses them does not run on the CMOS chips.

Variants and descendants

6507: the processor of the Atari 2600, a 6502 in a 28-pin package. It brings out 13 address lines, so it sees 8K, and has no IRQ or NMI pins. Atari’s Stella Programmer’s Guide gives its clock as “the 3.58 MHz oscillator divided by 3”, about 1.19 MHz.
6510: the Commodore 64’s version, with an I/O port at addresses 0 and 1. See the 6510 entry.
2A03: Ricoh’s chip for the NES, a 6502 core with the sound hardware on the same die. NESdev notes that it “lacks the MOS6502’s decimal mode”: the D flag can be set and read, but it has no effect.
65C02: a CMOS version designed by Mensch at his own company, the Western Design Center, and introduced in 1983. It adds 27 opcodes and two addressing modes to the original 151 opcodes, and fixes the JMP indirect bug, the decimal flags, the reset state of D and the stray indexed read. Apple used it in the Apple IIc, where its low power and low heat mattered.
65816: Mensch’s 16-bit extension, with a 24-bit address space and a 6502 emulation mode. It runs the Apple IIGS, at up to 2.8 MHz, and, as a custom 65C816 at 3.58 MHz, the Super Nintendo.

The machines

The 6502 was usually run at one or two million cycles a second, and the machine around it set the exact figure.

Machine	Processor and clock	Source
Apple II	6502 at 1.023 MHz	Apple II Reference Manual, 1979
Commodore PET	6502	Danton
Atari 2600	6507 at about 1.19 MHz	Stella Programmer’s Guide
Atari 400 and 800	6502 at 1.79 MHz	Atari 400/800 Hardware Manual
VIC-20	6502 at 1.02 MHz (NTSC)	COMPUTE!’s First Book of VIC
BBC Micro	6502 at 2 MHz, slowed to 1 MHz for slow peripherals	The Advanced User Guide for the BBC Micro
Commodore 64	6510 at 0.985 MHz (PAL) or 1.02 MHz (NTSC)	see the 6510 entry
NES	2A03 at 1.79 MHz (NTSC)	NESdev

The Atari 800’s clock was chosen so that “one machine cycle is equivalent in length to two color clocks”, and the 2600’s so that one cycle is three. Either way the processor’s timing is locked to the television picture, so a program can count cycles against the position of the beam.

The BBC Micro is the fast one. The Advanced User Guide explains that the 6502 “is operating at 2MHz”, but its clock “is stretched whenever 1MHz bus peripherals are being accessed”, so “the processor clock is only ever truly 2MHz when accessing main memory”.

The 6502 was still a job requirement in the mid-1990s. In April 1994 Edge’s recruitment pages carried a studio’s advertisement for “Programmers with Z80, 6502, 68000, 65816 experience”.

Sources

BYTE issue 3, November 1975, pp. 56-59: Daniel Fylstra, comparison of the Motorola 6800 and the MOS Technology 6500 series, with the introduction “Son of Motorola, or, the $20 CPU Chip”; the $150 previous low, the MCS6501 at $20 and MCS6502 at $25, the on-chip clock, the cycle counts, the hint of 2 or 3 MHz, and WESCON, San Francisco, 16-19 September.
BYTE, November 1982, p. 256: Phil Lemmons’s interview with Chuck Peddle; Peddle’s work on the 6800’s peripheral chips, the team taken to MOS in 1974, “chief architect in the design of the 6502”.
Tim Danton, The Computers That Made Britain (Raspberry Pi Press, 2021), chapter on the Commodore PET 2001: the 6800’s $300 price, the 6502’s lack of 16-bit operations, Motorola’s letter (quoting Peddle’s 2014 Computer History Museum oral history), John Paivinen, Mensch among the engineers who left Motorola, the lawsuit and the paperwork, the 6501 as a 6800 replacement, WESCON and the hotel suite, Wozniak and Jobs, the PET.
MOS Technology, MCS6500 Microcomputer Family Programming Manual, second edition, January 1976: zero page (§5.6, pp. 61-62); indexed addressing, the overlap, the incorrect-address reads and the zero-page wrap-around (§6.1-6.2, pp. 79-83); the stack in page one (§8.3, pp. 112-116); reset and its “automatic operations” (§9.2-9.3); the interrupt timings, JMP indirect (Example 9.6, p. 141) and the IRQ and NMI lines (§9.8-9.9); ROR “after June, 1976” (§10.4, p. 150); the instruction summary with its cycle counts and “Add 1 if page boundary is crossed” (appendix).
MOS Technology, MCS6500 Microcomputer Family data sheet: 1 MHz and 2 MHz timings, the IRQ, NMI, RDY and reset signal descriptions, the status register labels.
David Eyes and Ron Lichty, Programming the 65816, including the 6502, 65C02 and 65802 (Brady, 1986): Mensch as lead designer of the 6502 and designer of the 65C02, 65802 and 65816 (introduction); the JMP indirect bug, unused opcodes, decimal flags and reset state (pp. 43-44); the 65C02’s 27 new opcodes and two new addressing modes, the Apple IIc and IIe, and its fixes, including the indexed read (pp. 44-48); Table 4.6, differences between processors (151 opcodes, 56 mnemonics, D unknown after reset).
Apple Computer, Apple II Reference Manual (1979), chapter 6, “The Microprocessor”: MCS6502/SY6502 made by MOS Technology, Synertek and Rockwell; 56 instructions, 13 addressing modes, 1.023 MHz clock.
Atari, Stella Programmer’s Guide (1979), §3.2: the processor clock as the 3.58 MHz oscillator divided by 3.
Atari, Atari 400/800 Hardware Manual (1982), section II: “The 6502 microprocessor runs at 1.79 MHz”; one machine cycle equals two colour clocks.
COMPUTE!’s First Book of VIC (COMPUTE! Books, 1982): the VIC-20’s 1.02 MHz system clocks.
A.C. Bray, A.C. Dickens and M.A. Holmes, The Advanced User Guide for the BBC Micro (Cambridge Microcomputer Centre, 1983), the 1MHz bus: the 2 MHz processor clock and its stretching.
Apple Computer, Apple IIGS Hardware Reference (1988), chapter 10, “The 65C816 Microprocessor”, and the 2.8 MHz fast mode.
Nintendo Power issue 49, June 1993: Super NES CPU “Custom 65C816” at 3.58 MHz.
Sheldon Leemon, Mapping the 64 and 64C (COMPUTE! Books, 1987): locations 251-254, “Four Free Bytes of Zero Page for User Programs”.
groepaz, NMOS 6510 Unintended Opcodes: No More Secrets (December 2025): preface, scope (including the 6507’s 13 address lines and missing IRQ and NMI pins), the stable and unstable opcodes, and Wizball’s LAX #imm.
NESdev Wiki, “CPU” and “Status flags” (community reference, web, secondary): the 2A03 “lacks the MOS6502’s decimal mode”; B and bit 5 exist only in the pushed copy of P. https://www.nesdev.org/wiki/CPU
Edge issue 7, April 1994: recruitment advertisement asking for “Programmers with Z80, 6502, 68000, 65816 experience”.